Synopsys, a major supplier of electronic design automation (EDA) software and semiconductor intellectual property (IP), has developed a CXL 4.0 IP portfolio aimed at easing the memory bottlenecks facing AI infrastructure.
According to industry sources on Aug. 24, Synopsys recently announced its CXL 4.0 IP portfolio. Compute Express Link, or CXL, is an interconnect standard designed to link central processing units (CPUs), memory, storage and accelerators at high speed and with greater efficiency in high-performance computing systems. Because it builds on the PCI Express (PCIe) standard used to connect devices in PCs and servers, it offers broad interoperability.
The first CXL 1.0 specification was released in 2019 by a consortium initially led by Intel. Since then, not only CPU and graphics processing unit (GPU) suppliers but also memory makers have moved to develop products supporting the technology.
Chips supporting CXL 2.0 are already in mass production, while the industry is working toward adoption of CXL 3.0. Synopsys' decision to introduce CXL 4.0 IP ahead of broader market deployment is seen as an effort to establish an early lead. The CXL 4.0 standard was finalized late last year.
CXL 4.0 doubles the transfer rate to 128 GT/s from the previous generation and supports PCIe 7.0. Synopsys' CXL 4.0 IP integrates a controller, an Integrity and Data Encryption (IDE) security module, a silicon-proven physical layer and verification IP. It also supports interconnection with earlier CXL generations, broadening its potential range of applications.
Synopsys expects its CXL 4.0 IP to significantly accelerate memory access and utilization across AI infrastructure. The technology could provide a foundation for increasing memory capacity and bandwidth, which have emerged as major constraints for AI workloads.
“CXL will evolve from basic memory expansion to broad memory sharing and ultimately to fully disaggregated computing,” a Synopsys representative said. “CXL 4.0 will help move the industry toward full-scale disaggregated computing.”
