Cadence has developed a 3-nanometer memory subsystem IP for HBM4 and HBM4E that reaches 14 Gbps per pin in silicon validation, targeting a major bottleneck between AI accelerator system-on-chips and high-bandwidth memory.
The U.S. electronic design automation and semiconductor IP company said the new design has been validated with prototype silicon. It integrates the key components needed to connect an AI SoC with HBM, including the physical interface, or PHY, a memory controller and interconnect technology. In AI accelerators, this subsystem manages the high-speed signaling between a GPU or other compute chip and stacked HBM devices.
Cadence said the memory subsystem operated at 14 Gbps per pin in real-time memory-traffic testing in its lab environment, with no errors recorded across the round-trip path from the controller to the DRAM and back. That is roughly 1.5 times faster than the 8 Gbps to 9.6 Gbps-per-pin range associated with mainstream HBM3E products.
In separate transmitter, or TX, testing, Cadence achieved 16 Gbps per pin — the top data rate in the finalized HBM4 standard. Stress testing of the broader memory subsystem also maintained signal integrity at 18 Gbps, indicating additional performance headroom beyond the target operating speed.
The system also includes Cadence's proprietary silicon interposer design technology, intended to limit signal distortion and power loss during high-speed data transfers. In 2.5D packages, the silicon interposer routes signals between the HBM stacks and the processor's PHY. Cadence said the interposer has completed signal integrity, or SI, and power integrity, or PI, validation and will be available for HBM PHY licensees to use in their own AI SoC interposer designs.
Cadence said the new memory subsystem is designed to improve manufacturing yield and reliability for AI SoC developers, helping chipmakers overcome the “memory wall” that limits the performance of advanced AI accelerators.
