The demand for annealing, a critical thermal treatment process in semiconductor manufacturing, is rapidly expanding. Long a staple in silicon (Si) wafer production, the process is now migrating to silicon carbide (SiC), the cornerstone of next-generation power semiconductors. It is also poised to become a key enabler for advanced system semiconductors and next-generation memory, including NAND flash devices with more than 400 layers.
Industry sources report that Wolfspeed, the global leader in the SiC wafer market, is moving to integrate laser annealing equipment into its production lines. The company is said to be negotiating purchase orders (POs) with South Korean laser annealing partners, with plans to ramp up deployment following an initial small-batch introduction.
“We are seeing a definitive shift toward adopting annealing in SiC processes, where it was previously underutilized,” an industry insider noted. “The transition to 8-inch SiC wafers is providing a significant tailwind for the adoption of this equipment.”
Semiconductor annealing involves applying precise thermal energy to a wafer to repair lattice damage and activate implanted impurities, thereby enhancing electrical properties. While it is a standard post-ion implantation step for silicon, SiC has presented unique challenges. Unlike silicon, which is typically processed at around 1,000 °C, SiC requires temperatures exceeding 1,600 °C. This high thermal load has often led to interface damage or defects, hindering widespread adoption.
Recent advancements in laser technology, however, have changed the landscape. Modern laser annealing can target highly localized regions on nanosecond timescales, minimizing overall thermal stress on the wafer. This breakthrough has attracted interest not only from Wolfspeed but also from Samsung Electronics, which is reportedly considering the technology for its SiC foundry business, with mass production targeted by 2028.
Beyond power semiconductors, annealing is becoming indispensable for high-stack NAND flash. As manufacturers push toward 400-layer designs to increase capacity, they face the daunting task of etching deep “channel holes” through vertical memory cells. As these holes deepen, maintaining structural stability and electrical integrity becomes increasingly difficult. Localized crystallization via laser annealing is now being hailed as a key solution to reinforce these channel-hole regions.
The reach of this technology extends even further into the sub-2 nm logic domain. “There is a continuous industry effort to apply localized annealing to advanced system semiconductors at the 2 nm node and below,” another expert shared. “This diversification of annealing applications is expected to drive significant growth in the global laser solutions market.”
